Ghost

ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years

Cisco · Bangalore, India

A posting in this role has sat open 108 days — well past the 90-day mark where an opening reads as a resume black hole rather than an active search.

Posted (ATS)

5/8/2026, 12:00:00 AM

Updated (ATS)

5/8/2026, 12:00:00 AM

First seen by us

8/2/2026, 7:01:52 AM

Last re-seen

8/22/2026, 11:15:49 PM

Distinct job IDs

Open in parallel

Work locations

Cumulative days active

108

Stagnancy score

60.75

ATS job ID

2013406

Rotation timeline

Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.

Rotation 1LatestID 2013406Still openView listing →
Location
Bangalore, India
Posted (ATS)
May 8, 2026
Last confirmed open
Aug 22, 2026
Open for
107 days +

Data provenance

Source platform: workday
Source API URL: https://cisco.wd5.myworkdayjobs.com/wday/cxs/cisco/cisco_careers/jobs
Latest listing found: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Bangalore-India/ASIC-Engineering-Technical-Leader---Design-Verification---Verilog--System-Verilog--UVM--Testbench---Exp---12--Years_2013406
Stream ID: 1f25c4bd-11a6-495c-85e7-5ad19c9499d2

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