← Back to jobsPosted (ATS) 9/11/2026, 12:00:00 AM Updated (ATS) 9/11/2026, 12:00:00 AM First seen by us 9/11/2026, 5:00:46 PM Last re-seen 10/18/2026, 7:31:09 AM Distinct job IDs 3 Open in parallel 2 Work locations 1 Cumulative days active 102 Stagnancy score 45.56 ATS job ID JR0286860
FreshWithin normal posting window. For now.
Design Verification Engineer
Intel · US, California, Santa Clara
A posting in this role has sat open 62 days — past the 45-day mark where openings start to look less like an active, immediate need.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
These IDs appeared over a 65-day span, with only the latest still open — a sequential re-shelving pattern.
- Location
- US, California, Santa Clara
- Posted (ATS)
- Jul 8, 2026
- Ended (last seen)
- Jul 8, 2026
- Open for
- 1 day
- Location
- US, California, Santa Clara
- Posted (ATS)
- Jul 10, 2026
- Ended (last seen)
- Sep 7, 2026
- Open for
- 60 days
- Location
- US, California, Santa Clara
- Posted (ATS)
- Sep 11, 2026
- Last confirmed open
- Oct 18, 2026
- Open for
- 37 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://intel.wd1.myworkdayjobs.com/external/job/US-California-Santa-Clara/Design-Verification-Engineer_JR0286860
- Stream ID
- da50b648-11e1-4a39-a1d2-5b8e97fa91d7