← Back to jobsPosted (ATS) 5/21/2026, 12:00:00 AM Updated (ATS) 5/21/2026, 12:00:00 AM First seen by us 8/2/2026, 7:01:52 AM Last re-seen 8/22/2026, 11:15:49 PM Distinct job IDs 1 Open in parallel 1 Work locations 1 Cumulative days active 95 Stagnancy score 58.76 ATS job ID 2013039
GhostHigh-confidence zombie posting. HR is probably not actually hiring.
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)
Cisco · Pune, India
A posting in this role has sat open 95 days — well past the 90-day mark where an opening reads as a resume black hole rather than an active search.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
- Location
- Pune, India
- Posted (ATS)
- May 21, 2026
- Last confirmed open
- Aug 22, 2026
- Open for
- 94 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Pune-India/ASIC-Engineering-Design-Verification-Leader--SystemVerilog--Python--C-and-UVM--12-16-years--Pune-_2013039
- Stream ID
- 959f880e-7e49-41fc-b843-b64811202b32