← Back to jobsPosted (ATS) 8/7/2026, 12:00:00 AM Updated (ATS) 8/7/2026, 12:00:00 AM First seen by us 8/13/2026, 12:17:46 AM Last re-seen 8/22/2026, 12:46:04 AM Distinct job IDs 1 Open in parallel 2 Work locations 2 Cumulative days active 24 Stagnancy score 0 ATS job ID JR0285142
Multiple OpeningsSeveral job IDs open in parallel under one title — likely genuine multiple openings, not a recycled req.
Analog Layout Design Engineer
Intel · US, Oregon, Hillsboro
Posted across 2 work locations with little per-location re-posting — separate openings per region, not one recycled requisition.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
These IDs are spread across 2 different work locations — almost certainly separate openings per city/region, not one role re-posted over and over.
- Location
- Malaysia, Penang
- Posted (ATS)
- Jul 30, 2026
- Ended (last seen)
- Aug 17, 2026
- Open for
- 19 days
- Location
- US, Oregon, Hillsboro
- Posted (ATS)
- Aug 7, 2026
- Last confirmed open
- Aug 22, 2026
- Open for
- 15 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://intel.wd1.myworkdayjobs.com/external/job/US-Oregon-Hillsboro/Analog-Layout-Design-Engineer_JR0285142
- Stream ID
- 5eac2328-e5de-47d8-a44f-941b45208a82