← Back to jobsPosted (ATS) 8/10/2026, 12:00:00 AM Updated (ATS) 8/10/2026, 12:00:00 AM First seen by us 8/13/2026, 12:17:46 AM Last re-seen 10/18/2026, 9:00:43 AM Distinct job IDs 1 Open in parallel 1 Work locations 1 Cumulative days active 70 Stagnancy score 49.11 ATS job ID JR2023121
Suspected GhostRotation or age signals smell off. Proceed with skepticism.
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Nvidia · US, CA, Santa Clara
A posting in this role has sat open 70 days — past the 45-day mark where openings start to look less like an active, immediate need.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
- Location
- US, CA, Santa Clara
- Posted (ATS)
- Aug 10, 2026
- Last confirmed open
- Oct 18, 2026
- Open for
- 69 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://nvidia.wd5.myworkdayjobs.com/nvidiaexternalcareersite/job/US-CA-Santa-Clara/Senior-ASIC-Physical-Design-Engineer--Cache-Coherent-Interconnects_JR2023121
- Stream ID
- 9ad78ee0-e50b-4a16-8679-df4496cbf9d9