← Back to jobsPosted (ATS) 8/4/2026, 12:00:00 AM Updated (ATS) 8/4/2026, 12:00:00 AM First seen by us 8/13/2026, 12:17:46 AM Last re-seen 8/22/2026, 12:46:04 AM Distinct job IDs 2 Open in parallel 2 Work locations 2 Cumulative days active 23 Stagnancy score 0 ATS job ID JR0286250
Multiple OpeningsSeveral job IDs open in parallel under one title — likely genuine multiple openings, not a recycled req.
Semiconductor Device Modeling Engineer
Intel · US, California, Santa Clara
2 job IDs open in parallel rather than re-posted over time — most likely several genuine openings, not a recycle.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
These IDs are spread across 2 different work locations — almost certainly separate openings per city/region, not one role re-posted over and over.
- Location
- US, Oregon, Hillsboro
- Posted (ATS)
- Jul 31, 2026
- Last confirmed open
- Aug 22, 2026
- Open for
- 22 days +
- Location
- US, California, Santa Clara
- Posted (ATS)
- Aug 4, 2026
- Last confirmed open
- Aug 22, 2026
- Open for
- 18 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://intel.wd1.myworkdayjobs.com/External/job/US-California-Santa-Clara/Semiconductor-Device-Modeling-Engineer_JR0286250
- Stream ID
- 47efc5a4-c8d8-48d6-b0e0-2bbbde3fbef0