← Back to jobsPosted (ATS) 8/12/2026, 12:00:00 AM Updated (ATS) 8/12/2026, 12:00:00 AM First seen by us 8/13/2026, 12:17:46 AM Last re-seen 8/22/2026, 12:46:04 AM Distinct job IDs 3 Open in parallel 1 Work locations 2 Cumulative days active 59 Stagnancy score 44.22 ATS job ID JR0282539
FreshWithin normal posting window. For now.
Mixed Signal Logic Design Engineer
Intel · US, Oregon, Hillsboro
A posting in this role has sat open 59 days — past the 45-day mark where openings start to look less like an active, immediate need.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
These IDs are spread across 2 different work locations — almost certainly separate openings per city/region, not one role re-posted over and over.
- Location
- US, Oregon, Hillsboro
- Posted (ATS)
- Jun 25, 2026
- Last confirmed open
- Aug 22, 2026
- Open for
- 58 days +
- Location
- US, California, Folsom
- Posted (ATS)
- Jul 17, 2026
- Ended (last seen)
- Aug 17, 2026
- Open for
- 32 days
- Location
- US, Oregon, Hillsboro
- Posted (ATS)
- Aug 12, 2026
- Last confirmed open
- Aug 22, 2026
- Open for
- 10 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://intel.wd1.myworkdayjobs.com/External/job/US-Oregon-Hillsboro/Mixed-Signal-Logic-Design-Engineer_JR0282539
- Stream ID
- 807dd2fc-face-4b9a-8047-94aaa048ce71