Altera
198 active postings tracked via workday · 99 flagged suspicious
Large employer · high-volume employer (legitimately reposts more) · repeat offender
These measure different things: ghosty now is a snapshot of roles open today; lifetime ratespans every req ever posted (most of which closed normally), so the two aren’t a before-and-after. For when the freeze actually built up, see the timeline below.
When the freeze built up
Each bar is how many of Altera’s currently-open reqs — ones flagged ghost or suspected right now — first went up that year. Taller recent bars mean the freeze is still growing; the left bar is the long-frozen tail.
Describes the age of today’s open pile — not a historical rate. We’ve only tracked postings live since June 2026; earlier dates come from each req’s original post date.
- FPGA Silicon Design Verification Engineerghost · 81.06
- FPGA Silicon Design Verification Engineerfresh · 81.06
- Firmware Development Engineerghost · 80.76
- Analog Layout Design Engineerghost · 79.08
- FPGA Board Applications Engineerfresh · 77.85
- CAD Support - Studentghost · 77.55
- Product Development Engineerghost · 77.09
- Senior Technical Program Managerfresh · 76.48
- APAC Regional Trade Managerghost · 74.65
- Analog Layout Design Engineerfresh · 73.73
- Internal Sales Representativeghost · 70.37
- Senior / Principal GRC Analystghost · 68.69
- Senior Web Developerghost · 68.54
- Physical Design Engineerghost · 68.23
- FPGA Development Tools Engineerghost · 67.77
- Sales Account Managerghost · 67.16
- Director of Foundry Engineeringfresh · 67.01
- High Level Synthesis Compiler Engineerghost · 66.09
- Analog Circuit Design Engineerghost · 65.64
- Senior Aerospace, Defense, Government (ADG) Quality Management System Engineerghost · 65.64
- Senior OSAT Engineerghost · 65.48
- Senior Debug Verification Engineerfresh · 65.03
- FPGA Development Tools Engineerghost · 64.26
- Ethernet IP Design Application Engineerghost · 64.11
- CPU Design Verification Engineerghost · 63.8
- Sales Applications Engineerghost · 63.5
- IT End User Support Specialistghost · 63.35
- Principal NoC IP Micro-Architectghost · 63.35
- Static Timing Analysis (STA) Engineerghost · 63.35
- Software Engineering Manager - Graphical User Interface (GUI)fresh · 63.19
- DFT Architectghost · 63.04
- FPGA Silicon Design Engineersuspected_ghost · 62.73
- FPGA Silicon Design Engineersuspected_ghost · 62.73
- FPGA Compiler (Placer) Engineerghost · 62.28
- Engineering/IT Specialistghost · 61.97
- Post Silicon and System Validation Engineer Studentghost · 61.51
- IT & Audio Visual Support Specialistghost · 61.36
- SatCom, ISR & Space Payload Architectghost · 61.05
- SOC Frontend Integration Engineerghost · 61.05
- Senior Tax Analystghost · 60.9
- FPGA IP Software Development Engineersuspected_ghost · 60.44
- FPGA IP Software Development Engineersuspected_ghost · 60.44
- Workday Contractor - Recruiting Moduleghost · 60.29
- Senior Oracle Fusion Business Analyst – Invoice to Cashfresh · 59.53
- Director, Physical Designfresh · 59.37
- General Support Engineer – Aerospace, Defense & Government (ADG)ghost · 59.22
- Senior Physical Design Engineerghost · 59.22
- Signal Integrity/ Power Integrity Engineerghost · 59.07
- IT End User Support Specialistghost · 58.92
- Principal NoC IP Micro-Architectghost · 58.92
- Signal Integrity & Power Integrity Engineerghost · 58.92
- Functional Safety Architectghost · 58.76
- Senior Package Reliability Engineerghost · 58.76
- Physical Design Implementation and STA Leadghost · 58.61
- Physical Design Engineerghost · 58.61
- Physical Design Engineerghost · 58.61
- Student Signal and Power Integrity Engineerghost · 58.61
- SOC Timing Engineerghost · 58.46
- Senior Manufacturing and Supplier Quality Engineersuspected_ghost · 57.56
- FPGA Development Tools Engineerfresh · 55.78
- FPGA Development Tools Engineerfresh · 55.78
- Sr Salesforce Solution Architectsuspected_ghost · 54.89
- Analog Design Layout Managersuspected_ghost · 54.44
- Design Verification Engineersuspected_ghost · 54
- Data Engineersuspected_ghost · 54
- DDR Memory Interface System Validation Lead Engineersuspected_ghost · 53.11
- FPGA Compiler (Placer) Engineersuspected_ghost · 52.22
- Workday Contractor - Recruiting / Learning Modulessuspected_ghost · 51.78
- Customer Operations & Inside Sales Representativesuspected_ghost · 50.89
- Physical Design Engineersuspected_ghost · 50
- Physical Design Engineerfresh · 50
- Physical Design Engineersuspected_ghost · 50
- Cyber Resilience Act (CRA) Compliance Leadsuspected_ghost · 49.56
- FPGA Silicon Design Verification Engineersuspected_ghost · 48.67
- Wireline Marketing Manager (Routing/Switching, Security)suspected_ghost · 48.67
- GL Accounting Managersuspected_ghost · 48.22
- Senior Emulation Engineersuspected_ghost · 48.22
- FPGA System Design Engineersuspected_ghost · 47.78
- Senior FPGA Design Engineersuspected_ghost · 47.33
- Senior FPGA Design Engineersuspected_ghost · 47.33
- IP Firmware Design Engineersuspected_ghost · 46.89
- Software Validation Engineersuspected_ghost · 46.89
- Principal Network Security Engineerfresh · 46
- Software Product Managersuspected_ghost · 45.11
- FPGA Post Silicon Validation Engineer - HPS USBsuspected_ghost · 44.67
- Field Applications Engineer (FAE)suspected_ghost · 44.67
- Security Operations Center Leadfresh · 44.22
- Senior FPGA IP Solution Design Engineersuspected_ghost · 44.22
- Timing Engineersuspected_ghost · 44.22
- Inside Sales Representative (Sales)suspected_ghost · 44.22
- Product Physical Failure Analysis Engineersuspected_ghost · 44.22
- Product Failure Analysis Engineersuspected_ghost · 43.78
- Analog Layout Design Engineersuspected_ghost · 42.89
- Corporate Counselsuspected_ghost · 42.44
- FPGA Hardware Board Design Engineerfresh · 42.44
- Transceivers & Protocol IP Application Engineersuspected_ghost · 42
- Senior Backend Design Automation Engineer — New Process Node Enablementsuspected_ghost · 42
- Human Resources Global Services Specialistsuspected_ghost · 41.56
- FPGA Design Verification Engineersuspected_ghost · 41.56
- Staff Application Engineersuspected_ghost · 41.11
- Senior Field Sales Managersuspected_ghost · 41.11
- Analog Circuit Design Engineersuspected_ghost · 41.11
- Lead Product Plannerfresh · 39.78
- IP Applications Engineerfresh · 39.78
- Senior FPGA Development Kit Technical Lead Engineersuspected_ghost · 39.78
- Workday Integrations and Reporting Leadsuspected_ghost · 39.33
- FPGA Post Silicon Validation Engineer - Securitysuspected_ghost · 39.33
- FPGA Post Silicon Validation Engineer - Securitysuspected_ghost · 39.33
- Logic Designersuspected_ghost · 39.33
- Sales Account Managersuspected_ghost · 39.33
- Compute Interconnect IP Planner (Product Manager)fresh · 39.33
- Oracle Fusion ERP Order To Cash Business Analystsuspected_ghost · 39.33
- Sales Analystfresh · 38.44
- Sales Analystsuspected_ghost · 38.44
- Sales Applications Engineersuspected_ghost · 38.44
- Tax Analystsuspected_ghost · 38.44
- Field Application Engineersuspected_ghost · 38
- Junior Verification Engineersuspected_ghost · 38
- Software Engineer - Internmultiple_openings · 20.81
- Digital Design Verification Engineerfresh · 10.69
- FPGA IP Software Development Engineerfresh · 6.19
- Physical Design Engineer/STAfresh · 0
- Senior Mechanical Design Engineerfresh · 0
- System Level Test (SLT) Content Development and Debug Engineerfresh · 0
- Senior FPGA RTL and Firmware Development Engineerfresh · 0
- EDA Software Engineerfresh · 0
- Field Sales Technologistfresh · 0
- FPGA & Embedded SW Engineer – Aerospace & Defensefresh · 0
- Senior Director, Silicon Hardware Engineering - Boards, Packaging, & Reliabilityfresh · 0
- AI Engineer – Technical Leader (Agentic AI & FPGA Systems)fresh · 0
- Customer Operations & Inside Sales Representativefresh · 0
- DSP Specialist FAE (Field Applications Engineer) – West Regionfresh · 0
- Senior / Staff Embedded Applications Engineerfresh · 0
- Engineering Manager, FPGA Applications Engineeringfresh · 0
- Embedded IP Design Engineerfresh · 0
- Wireline Vertical Marketing Specialist (Routing/Switching, Security)fresh · 0
- Field Applications Engineer (FAE)multiple_openings · 0
- Field Applications Engineer (FAE)multiple_openings · 0
- Quartus Compiler Software - Internfresh · 0
- Senior Physical Design Engineerfresh · 0
- Field Sales Engineerfresh · 0
- Senior Tax Analyst, U.S. Tax Reporting & Compliancefresh · 0
- Senior/Staff Configuration Applications Engineerfresh · 0
- Senior HR Business Partner – India Leaderfresh · 0
- ITSM Operations Leadfresh · 0
- Silicon Domain Architectfresh · 0
- AI Lead Architect - Silicon Design Executionfresh · 0
- IP Logic Design Engineerfresh · 0
- FPGA IP Design and Verification Engineerfresh · 0
- Business Development Manager-Physical AIfresh · 0
- Government Program Control Analystfresh · 0
- Physical Design Lead — Executionfresh · 0
- Custom Analog Design Automation Leadfresh · 0
- Application Engineerfresh · 0
- Business Development Manager – Embeddedfresh · 0
- Senior QMS Engineerfresh · 0
- Senior Principal Engineerfresh · 0
- CPU Design Engineerfresh · 0
- AIOPs Observability/SRE Leadfresh · 0
- Workday Functional Solutions Architectfresh · 0
- AI Engineer – Cloud Software & AI Platforms - Contractfresh · 0
- Infrastructure Cyber Defense Leaderfresh · 0
- Senior Product Development Engineerfresh · 0
- Senior Director, Business Development – Physical AI, Robotics & Drones (Europe & APAC)fresh · 0
- DevSecOps and AI/Automation Engineerfresh · 0
- Product Architectural Model Development Leaderfresh · 0
- Lead Technical Program Managerfresh · 0
- Senior FPGA Silicon Validation Engineerfresh · 0
- MTS - Product Development Engineerfresh · 0
- Functional Safety Architectfresh · 0
- Senior FPGA IP Solutions Engineer – Robotics Technologyfresh · 0
- Program Manager, Government and Industryfresh · 0
- Senior Security Analyst: Assurance and Global Compliancefresh · 0
- Senior MTS - Product Development Engineerfresh · 0
- AI Architect, Agentic AI for Chip Design & EDAfresh · 0
- Commodity Managerfresh · 0
- Physical AI Solutions Architectfresh · 0
- Senior Financial Analyst - Engineering Financefresh · 0
- HW and DSP Graduate Internfresh · 0
- Full Chip Timing Modeling and Integration Engineerfresh · 0
- Security Operations Center Leadfresh · 0
- Identity and Data Cyber Defense Leadfresh · 0
- Endpoint and Data Security Engineerfresh · 0
- Senior DFT Design Engineerfresh · 0
- DFT Design Engineerfresh · 0
- Cyber Offense, SOC, and IR Leadfresh · 0
- Staff Application Engineerfresh · 0
- High Level Synthesis (HLS) Compiler Engineer (Intern))fresh · 0
- Undergrad Intern Technicalfresh · 0
- Principal/Senior Principal Engineer - Physical Design Implementation and Signoff Methodologyfresh · 0
- Software Enabling and Optimization Engineerfresh · 0
- FPGA IP Design Engineer - Internfresh · 0
- Senior Financial Analystfresh · 0
- Senior Manager, Global Consolidationfresh · 0
- FPGA Silicon Validation Engineerevergreen · 0
- FPGA Design Applications Engineerfresh · 0
- Senior Director, Silicon Architecture and Design Engineering (Ethernet/PCIe Center of Excellence))fresh · 0
- FPGA Silicon Validation Engineerfresh · 0