← Back to jobsPosted (ATS) 10/15/2026, 12:00:00 AM Updated (ATS) 10/15/2026, 12:00:00 AM First seen by us 10/16/2026, 7:30:44 PM Last re-seen 10/18/2026, 9:15:39 PM Distinct job IDs 1 Open in parallel 1 Work locations 1 Cumulative days active 4 Stagnancy score 0 ATS job ID R03324
FreshWithin normal posting window. For now.Repeat offender company
FPGA IP Design Engineer - Intern
Altera · Toronto, Ontario, Canada
Within normal posting window. For now.
Rotation timeline
Every ATS job ID we've matched to this same normalized title, oldest first. "Posted" is the date the ATS reports; "last confirmed open" is the last time we saw it live.
- Location
- Toronto, Ontario, Canada
- Posted (ATS)
- Oct 15, 2026
- Last confirmed open
- Oct 18, 2026
- Open for
- 4 days +
Data provenance
- Source platform
- workday
- Latest listing found
- https://altera.wd1.myworkdayjobs.com/Altera/job/Toronto-Ontario-Canada/FPGA-IP-Design-Engineer----Intern_R03324
- Stream ID
- 260f9c1c-a6b5-4a91-9b99-8f4077ae7829